Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable system on a chips (FPSCs), or other types of programmable devices) may be configured to implement user-specified functionality. Conventionally, a user design is realized by mapping a synthesized design to a netlist of components, logically packing the netlist components together, assigning the netlist components to particular physical locations in a PLD (e.g., placement), and then routing signal paths between the physical locations.
Component placement is particularly important, as this greatly affects signal path timing. Conventional design processes typically rely on time estimates that are based on logic-level operations (e.g., logic-level delay estimation). However, such estimated timing is often inaccurate, as it does not account for the actual physical positions of the components within the PLD, and fails to consider the impact of previously placed components on newly placed components.
Some conventional techniques attempt to mitigate these difficulties by permitting the user to specify particular components to be grouped together to improve timing. However, such techniques may require significant user effort to manage and monitor the placement of the grouped components. Thus, there is a need for an improved approach to component placement in PLDs.
Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.